Exploiting on-chip inductance in high speed clock distribution networks

Midwest Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages 1236-1239

  Ismail, Yehea I ^a   Friedman, Eby G ^b   Neves, Jose L ^c  

^a NORTHWESTERN UNIVERSITY   (United States)

^b UNIVERSITY OF ROCHESTER   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER SUPPLIES TO APPARATUS; INDUCTANCE; OPTIMIZATION; SHORT CIRCUIT CURRENTS;

HIGH SPEED CLOCK DISTRIBUTION NETWORKS; ON-CHIP INDUCTANCE; SIGNAL SLEW RATE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034465442     PISSN: 15483746     EISSN: None     Source Type: Journal    
DOI: 10.1109/SIPS.2000.886762     Document Type: Article

References (31)

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