Low power digital CMOS buffer systems for driving highly capacitive interconnect lines

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages 362-365

  Secareanu, Radu M ^b   Friedman, Eby G ^a  

^a University of Rochester   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CAPACITANCE; DIGITAL CIRCUITS; ELECTRIC POTENTIAL; ELECTROMIGRATION; LOGIC GATES; SPURIOUS SIGNAL NOISE;

DEEP SUBMICROMETER; HIGHLY CAPACITATIVE INTERCONNECT LINES; SWITCHING NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0034464356     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/MWSCAS.2000.951661     Document Type: Article

References (11)

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6. Design of tapered buffers with local interconnect capacitance
7. Repeater design to reduce delay and power in resistive interconnect
8. Delay and power expressions for a CMOS inverter driving a resistive-capacitive load
9. Repeater insertion to reduce delay and power in RC tree structures
10. Optimum buffer circuits for driving long uniform lines
11. Exploiting hysteresis in a CMOS buffer