Building reliability into full-array BGAs

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2000, Pages 146-152

  Li, Yuan ^a   Pannikkat, Anil ^a   Anderson, Larry ^a   Verma, Tarun ^a   Euzent, Bruce ^a  

^a ALTERA CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; GATES (TRANSISTOR); INTERFEROMETRY; RELIABILITY; THERMAL EXPANSION;

COEFFICIENT OF THERMAL EXPANSION; MOIRE INTERFEROMETRY; PACKAGE RELIABILITY;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034449522     PISSN: 10898190     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEMT.2000.910723     Document Type: Article

References (4)

1. ACES of finite element and life prediction models for solder joint reliability
2. Effect of test board design on the 2nd level reliability of a fine pitch BGA package
3. The effect of PBGA solder pad geometry on solder joint reliability SMI