High-performance low-power polyphase channelizer chip-set

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2000, Pages 1691-1694

  Song, William S ^a   Vai, Michael M ^a   Nguyen, Huy T ^a   Horst, Albert H ^a  

^a MIT LINCOLN LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; DIGITAL FILTERS; FAST FOURIER TRANSFORMS; PARALLEL PROCESSING SYSTEMS; RADAR SYSTEMS;

POLYPHASE FILTERS;

SIGNAL PROCESSING;

EID: 0034445812     PISSN: 10586393     EISSN: None     Source Type: Journal    
DOI: 10.1109/ACSSC.2000.911277     Document Type: Article

References (6)

1. R. E. Crochiere L. R. Rabiner Multirate Digital Signal Processing Prentice-Hall Signal Processing Series 1983
2. C. L. Wang C. H. Wei S. H. Chen Efficient Bit-Level Systolic Array Implementation of FIR and IIR Digital Filters IEEE Journal on Selected Areas in Communications 6 3 April 1988
3. W. S. Song A Two Trillion Operations per Second Miniaturized Mixed Signal Radar Receiver/Processor Asilomar Conference on Signals, Systems, and Computers 1542 1546 Asilomar Conference on Signals, Systems, and Computers 1997-November
4. W. S. Song A New 3-GSPS 65-GOPS UHF Digital Radar Receiver and Its Performance Characteristics Asilomar Conference on Signals, Systems, and Computers 1542 1546 Asilomar Conference on Signals, Systems, and Computers 1997-November
5. W. S Song All-Digital Radar Receiver Government Microcircuit Applications Conference 51 54 Government Microcircuit Applications Conference 1996-March
6. W. S. Song VLSI Bit-level Systolic Array for Radar Frontend Signal Processing Asilomar Conference on Signals, Systems, and Computers 1407 1411 Asilomar Conference on Signals, Systems, and Computers 1994-October