The implementation of a COTS based fault tolerant avionics bus architecture

IEEE Aerospace Conference Proceedings

Volumn 7, Issue , 2000, Pages 297-305

  Chau, S ^a   Luong, H ^a   Charlan, W ^a   Fukuhara, R ^a   Holmberg, E ^a   Jones, P ^a   Pixler, G ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AVIONICS; INTERFACES (COMPUTER); SPACE FLIGHT; SPACECRAFT; STANDARDS;

COMMERCIAL OFF THE SHELF; FAULT TOLERANT AVIONICS BUS ARCHITECTURE; PERIPHERAL COMPONENT INTERFACE BUS;

AEROSPACE ENGINEERING;

EID: 0034431835     PISSN: 1095323X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. NASA center for integrated space microsystems
2. Building standard based COTS multiprocessor computer systems for space around a high speed serial bus network
3. Cassini orbiter functional requirements book: Command and data subsystem
4. COTS-based fault tolerance in deep space: Qualitative and quantitative analyses of a bus network architecture
5. X2000 first delivery digital input and output (DIO) ASIC
6. The design of a fault-tolerant cots-based bus architecture
7. X2000 integrated first delivery project mixed- Signal input/output (MSIO) ASIC requirements
8. X2000 MSIO/DIO transformer interface isolator specification