A 600MHz 64b PA-RISC microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 94-95

  Hurd, K A ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ASYNCHRONOUS TRANSFER MODE; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; CRITICAL PATH ANALYSIS; FIRMWARE; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTING SILICON; TIMING CIRCUITS;

BUS TRANSACTIONS; REPLACEMENT ALGORITHMS;

MICROPROCESSOR CHIPS;

EID: 0034431133     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 500MHz 64b RISC CPU with 1.5MB on-chip cache
2. A quad-issue out-of-order RISC CPU
3. A 500MHz 1.5MB cache with on-chip CPU
4. Advanced performance features of the 64-bit PA-8000