Using wafer-scale patterns for CMP analysis

Materials Research Society Symposium - Proceedings

Volumn 613, Issue , 2000, Pages E8.8.1-E8.8.5

  Lee, Brian ^a   Gan, Terence ^a   Boning, Duane S ^a   David, Jeffrey ^b   Bonner, Benjamin A ^b   McKeever, Peter ^b   Osterheld, Thomas H ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; LIGHT POLARIZATION; LITHOGRAPHY; MASKS;

WAFER SCALE PATTERNS;

WSI CIRCUITS;

EID: 0034428372     PISSN: 02729172     EISSN: None     Source Type: Journal    
DOI: 10.1557/proc-613-d11.8.1/e8.8.1     Document Type: Article

References (8)

1. An integrated characterization and modeling methodology for CMP dielectric planarization
2. A CMP model combining density and time dependencies
3. A production-proven Shallow Trench Isolation (STI) solution using novel CMP concepts
4. Wear-contact problems and modeling of chemical-mechanical polishing
5. Three-dimensional chemical-mechanical polishing process model by BEM
6. Wafer flatness requirements for future technologies
7. Nanotopology effects in chemical mechanical polishing