8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2RAM)

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1668-1672

  Agata, Yasuhiro ^a,b,c   Motomochi, Kenji ^a   Fukushima, Yoshifumi ^a   Shirahama, Masanori ^a   Kurumada, Marefusa ^a   Kuroda, Naoki ^a   Sadakata, Hiroyuki ^a   Hayashi, Kohtaro ^a   Yamada, Toshio ^a   Takahashi, Kazunari ^a   Fujita, Tsutomu ^a  

^a PANASONIC CORPORATION   (Japan)

^b KOBE UNIVERSITY   (Japan)

^c Kyoto Semiconductor Corporation   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITORS; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; DATA PROCESSING; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS;

DUAL PORT INTERLEAVED DRAM ARCHITECTURE; OPEN BITLINE; PIPELINED OPERATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034316832     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881213     Document Type: Article

References (5)

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