New timing-driven placement algorithm based on table-lookup delay model

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

Volumn 21, Issue 11, 2000, Pages 1129-1138

  Yu, H ^a   Hong, X L ^a   Yao, B ^a   Cai, Y C ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Clustering; Quadratic placement; Table lookup; Timing

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; NONLINEAR PROGRAMMING; TIME SHARING PROGRAMS;

QUADRATIC PLACEMENT; TABLE LOOKUP;

VLSI CIRCUITS;

EID: 0034312054     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (10)

1. Efficient placement algorithms optimizing delay for high-speed ECL masterslice LST's
2. An adaptive timing-driven layout for high speed VLSI
3. Timing-driven layout of cell-based IC's
4. Chip layout optimization using critical path weighting
5. Performance-driven placement of cell based IC'S
6. Performance driven macro-cell placement algorithm
7. RITUAL: A performance driven placement algorithm for small cell ICs
8. VEAP: A global optimization based placement algorithm for standard cell design
9. CASH: A novel quadratic placement algorithm for very large standard cell layout design based on clustering