메뉴 건너뛰기




Volumn 16, Issue 5, 2000, Pages 443-451

Algorithms to select IDDQ measurement vectors for bridging faults in sequential circuits

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENT MEASUREMENT; ELECTRIC NETWORK ANALYSIS; HEURISTIC METHODS; VECTORS;

EID: 0034298662     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008360430959     Document Type: Article
Times cited : (1)

References (12)
  • 2
    • 0029212743 scopus 로고
    • CURRENT: A Test Generation System for IDDQ Testing
    • U. Mahlstedt, J. Alt, and M. Heinitz, "CURRENT: A Test Generation System for IDDQ Testing," Proc. VLSI Test Symp., 1995, pp. 317-323.
    • (1995) Proc. VLSI Test Symp. , pp. 317-323
    • Mahlstedt, U.1    Alt, J.2    Heinitz, M.3
  • 3
    • 0030399159 scopus 로고    scopus 로고
    • Driving Toward Higher IDDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG
    • H. Kondo and K.-T. Cheng, "Driving Toward Higher IDDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG," Dig. Int. Conf. on Computer-Aided Design, 1996, pp. 228-232.
    • (1996) Dig. Int. Conf. on Computer-Aided Design , pp. 228-232
    • Kondo, H.1    Cheng, K.-T.2
  • 4
    • 0030381187 scopus 로고    scopus 로고
    • An Efficient Compact Test Generator for IDDQ Testing
    • H. Kondo and K.-T. Cheng, "An Efficient Compact Test Generator for IDDQ Testing," Proc. Asian Test Symp., 1996, pp. 177-182.
    • (1996) Proc. Asian Test Symp. , pp. 177-182
    • Kondo, H.1    Cheng, K.-T.2
  • 5
    • 0032307486 scopus 로고    scopus 로고
    • A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults
    • T. Shinogi and T. Hayashi, "A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults," Proc. VLSI Test Symp., 1998, pp. 112-117.
    • (1998) Proc. VLSI Test Symp. , pp. 112-117
    • Shinogi, T.1    Hayashi, T.2
  • 9
    • 0032735596 scopus 로고    scopus 로고
    • Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits
    • Y. Higami, K.K. Saluja, and K. Kinoshita, "Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits," Proc. VLSI Design Conf., 1999, pp. 72-77.
    • (1999) Proc. VLSI Design Conf. , pp. 72-77
    • Higami, Y.1    Saluja, K.K.2    Kinoshita, K.3
  • 10
    • 0343759492 scopus 로고
    • Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits
    • S. Chakravarty and P.J. Thadikaran, "Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits," Proc. VLSI Test Symp., 1993, pp. 25-32.
    • (1993) Proc. VLSI Test Symp. , pp. 25-32
    • Chakravarty, S.1    Thadikaran, P.J.2
  • 11
    • 0029713581 scopus 로고    scopus 로고
    • Genetic-Algorithm-Based Test Generation for Current Testing of Bridging Faults in CMOS VLSI Circuits
    • T. Lee, I.N. Hajj, E.M. Rundnick, and J.H. Patel, "Genetic-Algorithm-Based Test Generation for Current Testing of Bridging Faults in CMOS VLSI Circuits," Proc. VLSI Test Symp., 1996, pp. 456-462.
    • (1996) Proc. VLSI Test Symp. , pp. 456-462
    • Lee, T.1    Hajj, I.N.2    Rundnick, E.M.3    Patel, J.H.4
  • 12
    • 0031356195 scopus 로고    scopus 로고
    • Sequential Circuit Test Generation for IDDQ Testing of Bridging Faults
    • Y. Higami, T. Maeda, and K. Kinoshita, "Sequential Circuit Test Generation for IDDQ Testing of Bridging Faults," Dig. Int. Workshop on IDDQ Testing, 1997, pp. 12-16.
    • (1997) Dig. Int. Workshop on IDDQ Testing , pp. 12-16
    • Higami, Y.1    Maeda, T.2    Kinoshita, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.