Minority-carrier lifetime optimization in silicon MOS devices by intrinsic gettering

Journal of Crystal Growth

Volumn 218, Issue 2, 2000, Pages 239-244

  Choe, Kwang Su ^a   Jang, Byung Nam ^a  

^a Suwon University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COMPUTER SIMULATION; CRYSTAL DEFECTS; GETTERS; MAGNETIC FIELDS; PRECIPITATION (CHEMICAL); SILICON WAFERS; SUBSTRATES;

INTRINSIC GETTERING METHOD; MINORITY-CARRIER LIFETIME;

MOS DEVICES;

EID: 0034273164     PISSN: 00220248     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0022-0248(00)00552-2     Document Type: Article

References (6)

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3. Lefevre H. J. Appl. Phys. 22:1980;15.
4. H.R. Huff, Solid State Technology, February 1983, p. 89.
5. ASTM Standard F121, 1988 Annual Book of ASTM Standards, Am. Soc. Test. Mat., Philadelphia, PA, 1988.
6. Jastrzebski L., Soydan R., McGinn J., Kleppinger R., Blumenfeld M., Gillespie G., Armour N., Goldsmith B., Henry W., Vecrumba S. J. Electrochem. Soc. 134:1987;1018.