Parallel image processing with the block data parallel architecture

IBM Journal of Research and Development

Volumn 44, Issue 5, 2000, Pages 681-702

  Alexander, Winser E ^a   Reeves, Douglas S ^a   Gloster Jr , Clay S ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; COSINE TRANSFORMS; DATA COMMUNICATION SYSTEMS; DATA FLOW ANALYSIS; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; MATRIX ALGEBRA; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

BLOCK DATA FLOW PARADIGM (BDFP); CHOLESKY FACTORIZATION;

IMAGE PROCESSING;

EID: 0034266785     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.445.0681     Document Type: Article

References (69)

1. W. Sung, S. K. Mitra, and B. Jeren, "Multiprocessor implementation of digital filtering algorithms using a parallel block processing model," IEEE Trans. Parallel and Distrib. Syst., vol. 3, 1992.
2. T. P. Barnwell III, V. K. Madisetti, and S. J. McGrath, "The Georgia Tech digital signal multiprocessor," IEEE Trans. Signal Process., vol. 41, no. 7, 1993.
3. S. Y. Kung, VLSI Array Processors. Englewood Cliffs, NJ: Prentice-Hall, 1988.
4. S. Sunder and V. Ramachandran, "Systolic implementation of multidimensional nonrecursive digital filters," IEEE Trans. Circ. and Syst. for Video Technol., vol. 3, pp. 399-407, 1993.
5. C. W. Wu, "Bit-level pipelined 2-D digital filters for real-time image processing," IEEE Trans. Circ. and Syst. for Video Technol., vol. 1, pp. 22-34, 1991.
6. D. Dudgeon and R. Mersereau, Multidimensional Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1984.
7. D. A. Gajski, D. A. Padua, D. J. Kuck, and R. H. Kuhn, "A second opinion on data flow machines and languages," Computer, vol. 15, pp. 58-69, 1982.
8. B. C. Kuo, Digital Control Systems. New York: Holt, Rinehart and Winston, 1980.
9. J. H. Kim and W. E. Alexander, "A multiprocessor architecture for two-dimensional digital filters," IEEE Trans. Comput., vol. C-36, pp. 876-884, 1987.
10. W. E. Alexander and C. J. Ju, "Considerations for the block state implementation of multidimensional digital filters," in Proc. Asilomar Conf. on Signals, Syst. and Comput., 1987.
11. R. Roesser, "A discrete state space model for linear image processing," IEEE Trans. Autom. Contr., vol. AC-20, pp. 1-10, 1975.
12. E. Fomasini and G. Maresini, "State space realization theory for two dimensional filters," IEEE Trans. Autom. Contr., vol. AC-21, pp. 484-492, 1976.
13. M. R. Azimi-Sadjadi and R. A. King, "Two-dimensional block processor-structures and implementations," IEEE Trans. Circ. and Syst., vol. CAS-33, pp. 42-50, 1986.
14. C. J. Ju and W. E. Alexander, "Block realization of multidimensional IIR digital filters and its finite word length effects," IEEE Trans. Circ. and Syst., vol. CAS-34, pp. 1030-1044, 1987.
15. S. Y. Kung, S. C. Lo, S. N. Jean, and J. N. Hwang, "Wavefront array processor-Concept to implementation," Computer, vol. 20, no. 7, pp. 18-33, 1987.
16. M. C. Chen, Y. Choo, and J. Li, "Compiling parallel programs by optimizing performance," J. Supercomput., vol. 2, pp. 171-207, Oct. 1988.
17. M. Gupta and P. Banerjee, "Demonstration of automatic data partitioning techniques for parallelizing compilers on multicomputers," IEEE Trans. Parallel and Distrib. Syst., vol. 3, pp. 179-193, Mar. 1992.
18. P. H. Hartel, H. Glaser, and J. M. Wild, "Compilation of functional languages using flow graph analysis," Software-Practice and Experience, vol. 24, no. 2, pp. 127-173, Feb. 1994.
19. J. Ramanujam, "Compile-time techniques for data distribution in distributed memory machines," IEEE Trans. Parallel and Distrib. Syst., vol. 2, pp. 472-482, Oct. 1991.
20. F. Gasperoni and U. Schwiegelshohn, "Scheduling loops on parallel processors: A simple algorithm with close to optimum performance," Lecture Notes in Computer Sci., no. 634, pp. 625-636, 1992.
21. K. Hwang, Advanced Computer Architecture With Parallel Programming. San Francisco: McGraw-Hill, 1993.
22. K. K. Parhi and D. G. Messerschmitt, "Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding," IEEE Trans. Comput., vol. 40, pp. 178-195, Feb. 1991.
23. C. M. Wang and S. D. Wang, "Efficient processor assignment algorithms and loop transformations for executing nested parallel loops on multiprocessors," IEEE Trans. Parallel and Distrib. Syst., vol. 3, pp. 71-82, Jan. 1992.
24. M. E. Wolfe and M. S. Lam, "A loop transformation theory and an algorithm to maximize parallelism," IEEE Trans. Parallel and Distrib. Syst., vol. 2, pp. 452-471, Oct. 1991.
25. M. C. Chen and C. E. Mead, "Concurrent algorithm as space-time recursion equations," in Proc. USC Workshop VLSI Modern Signal Process., Nov. 1982, pp. 31-52.
26. V. Van Dongen and P. Quinton, "The mapping of linear recurrence equations on regular arrays," J. VLSI Signal Process., vol. 1, pp. 95-113, 1989.
27. L. Johnsson and D. Cohen, "A mathematical approach to modeling the flow of data and control in computational networks," in CMU Conf. VLSI Syst. and Computers, Oct. 1981, pp. 226-234.
28. W. L. Miranker and A. Winkler, "Spacetime representations of computational structures," Computing, vol. 32, pp. 93-114, 1984.
29. P. Quinton, "Automatic synthesis of systolic arrays from uniform recurrence equations," in Proc. 11th Annu. Symp. Comput. Architecture, 1984, pp. 208-214.
30. R. Cole and U. Vishkin, "Approximate and exact parallel scheduling with applications to list, tree, and graph problems," in Proc. 27th Annu. Symp. on Found, of Computer Sci., New York, 1986, pp. 478-491.
31. K. Efe, "Heuristic models of task assignment scheduling in distributed systems," IEEE Computer, pp. 50-56, June 1982.
32. S. H. Huang and J. M. Rabaey, "Maximizing the throughput of high performance DSP applications using behavioral transformations," in Proc. Europe. Design and Test Conf., 1994, pp. 25-30.
33. W. Shen and D. Sweeting, "Heuristic algorithms for task assignment and scheduling in a processor network," Parallel Computing, vol. 20, no. 1, pp. 1-14, Jan. 1994.
34. B. A. Curtis and V. K. Madisetti, "Rapid prototyping on the Georgia Tech digital signal multiprocessor," IEEE Trans. Signal Process., vol. 42, pp. 649-662, Mar. 1994.
35. P. R. Gelabert and T. P. Barnwell III, "Optimal automatic periodic multiprocessor scheduler for fully specified flow graphs," IEEE Trans. Signal Process., vol. 41, pp. 858-888, Feb. 1993.
36. S. M. H. de Groot, S. H. Gerez, and O. E. Herrmann, "Range-chart-guided iterative data-flow graph scheduling," IEEE Trans. Circ. and Syst., vol. 39, pp. 351-364, May 1992.
37. M. Renfors and Y. Neuvo, "The maximum sampling rate of digital filters under speed constraints," IEEE Trans. Circ. and Syst., vol. 28, pp. 196-202, 1981.
38. K. Hwang, Y. H. Cheng, F. D. Angers, and C. Y. Lee, "Scheduling precedence graphs in systems with interprocessor communication," SIAM J. Computing, vol. 18, pp. 244-257, 1989.
39. M. Potkonjak and J. M. Rabaey, "Scheduling algorithms for hierarchical data control flow graphs," Int. J. Circ. Theory and Applicat., vol. 20, pp. 217-233, 1992.
40. S. Dandamudi, "A comparison of task scheduling strategies for multiprocessor systems," in Proc. 3rd IEEE Symp. on Parallel and Distrib. Process., 1991, pp. 423-426.
41. K. Konstantinides, R. T. Kaneshiro, and J. R. Tani, "Task allocation and scheduling models for multiprocessor digital signal processing," IEEE Trans. Signal Process., vol. 38, Dec. 1990.
42. C. S. R. Krishnan, D. A. L. Piriyakumar, and C. S. R. Murthy, "Task allocation and scheduling models for multiprocessor digital signal processing," IEEE Trans. Signal Process., vol. 43, no. 3, pp. 802-805, Mar. 1995.
43. S. Manoharan and N. P. Topham, "An assessment of assignment schemes for dependency graphs," Parallel Computing, vol. 21, no. 1, pp. 85-107, Jan. 1995.
44. C. L. McCreary, A. A. Khan, J. J. Thompson, and M. E. McArdle, "A comparison of heuristics for scheduling dags on multiprocessors," in Proc. 8th Int. Parallel Process. Symp., 1994, pp. 446-451.
45. C. E. Leiserson and J. B. Saxe, Retiming Synchronous Circuitry. Palo Alto, CA: Syst. Res. Ctr., 1989.
46. A. Aho, J. Hopcroft, and J. Ullman, The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974.
47. G. R. Cato and D. S. Reeves, "Parallel task scheduling using the order graph method," in Proc. 1995 IEEE 14th Annu. Int. Pheonix Conf. on Computers and Commun., Mar. 1995, pp. 69-75.
48. Y. L. Varol and D. Rotem, "An algorithm to generate all topological sorting arrangements," Computer J., vol. 24, pp. 83-84, 1981.
49. S. M. Park et al., "A novel VLSI architecture for the real-time implementation of 2-D signal processing systems," in Proc. IEEE Int. Conf. on Compter Design: VLSI in Computers and Processors, 1988.
50. M. Y. Dabbagh and W. E. Alexander, "Frequency domain implementation of block state space 2-D digital filters," in Proc. 31st Midwest Symp. on Circ. and Syst., 1988.
51. _, "VLSI multiprocessor implementation of block state-space digital filters," in Proc. Int. Symp. on Circ. and Syst., 1989.
52. _, "Multiprocessor implementation of 2-D denominator-separable digital filters for real-time processing," IEEE Trans. Acoust., Speech, Signal Process., vol. 37, pp. 872-881, June 1989.
53. H. Xu and W. E. Alexander, "A high performance architecture for real-time signal processing and matrix operations," in Proc. 1992 IEEE Int. Symp. on Circ. and Syst., 1992, pp. 1057-1060.
54. S. A. Howard and W. E. Alexander, "Simulation and performance evaluation of a parallel architecture for signal processing," in Proc. Southeast. Symp. on Syst. Theory, Mar. 1994, pp. 82-85.
55. S. Alexandre, W. Alexander, and D. Reeves, "A programmable simulator for analyzing the block data flow architecture," in Proc. 2nd Workshop on Modeling, Analysis, and Simulation of Computer and Telecommun. Syst. (MASCOTS'94), 1994, IEEE Computer Soc. Press.
56. P. Beadle, C. Pommerell, and M. Annaratone, "K9: A simulator of distributed-memory parallel processors," in IEEE Proc. Supercomputing '89, 1989, pp. 765-774.
57. S. Mehrotra,"Developing a simulator for the USC orthogonal multiprocessor," in Proc. 1990 Winter Simulation Conf., 1990, pp. 857-862.
58. C. S. Lee and R. J. Evans, "A new eigenvector weighting method for stable high resolution array processing," IEEE Trans. Signal Process., vol. 40, no. 4, pp. 999-1004, 1992.
59. C. L. Nikias and M. I. Guerlli, "An eigenvector-based algorithm for multichannel blind deconvolution of input colored signals," IEEE Trans. Signal Process., vol. 43, pp. 134-149, 1995.
60. Y. T. Chang and J. J. Leou, "New sytstolic array implementation of the 2-D discrete cosine transform and its inverse," IEEE Trans. Circ. and Syst. for Video Technol., vol. 5, pp. 150-157, 1995.
61. A. Madisetti and A. N. Wilson, "A 100 MHz 2-D 8 × 8 DCT/IDCT processor for HDTV applications," IEEE Trans. Circ. and Syst. for Video Technol., vol. 5, pp. 158-165, 1995.
62. R. S. Martin, G. Peters, and J. H. Wilkinson, "Symmetric decomposition of a positive definite matrix," Numerical Math, pp. 362-383, 1965.
63. G. H. Golub and C. F. Van Loan, Matrix Computations. Baltimore: Johns Hopkins, 1989, ch. 4, pp. 139-149.
64. J. J. Dongarra, I. S. Duff, D. C. Sorensen, and H. A. van der Vorst, Solving Linear Systems on Vector and Shared Memory Computers, Soc. Indust. and Appl. Math., chs. 5 and 6, pp. 75-142, 1991.
65. M. Lu, "A toeplitz-induces mapping technique in sensor array processing," IEEE Trans. Signal Process., vol. 43, pp. 1128-1139, 1995.
66. C. E. Davila and H. Chiang, "An algorithm for ploe-zero system model order estimation," IEEE Trans. Signal Process., vol. 43, pp. 1013-1017, 1995.
67. W. K. Pratt, Digital Image Processing. New York: Wiley Interscience, 1978.
68. Z. Fu and E. M. Dowling, "Conjugate gradient eigenstructure tracking for adaptive spectral estimation," IEEE Trans. Signal Process., vol. 43, pp. 1151-1160, 1995.
69. W. Lu, H. Wang, and A. Antoniou, "Design of two-dimensional FIR digital filters using the singular-value decomposition," IEEE Trans. Circ. and Syst., vol. 37, pp. 35-45, 1990.