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Volumn 10, Issue 5, 2000, Pages 782-796

Hardware and software cache prefetching techniques for MPEG benchmarks

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SOFTWARE; PARALLEL PROCESSING SYSTEMS; STANDARDS; STORAGE ALLOCATION (COMPUTER);

EID: 0034245755     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.856455     Document Type: Article
Times cited : (35)

References (16)
  • 1
    • 0002517538 scopus 로고    scopus 로고
    • MMX technology extension to the intel architecture
    • Aug.
    • A. Peleg and U. Weiser, "MMX technology extension to the intel architecture," IEEE Micro, vol. 16, pp. 51-59, Aug. 1996.
    • (1996) IEEE Micro , vol.16 , pp. 51-59
    • Peleg, A.1    Weiser, U.2
  • 2
    • 0020177251 scopus 로고
    • Cache memories
    • Sept.
    • A. J. Smith, "Cache memories," ACM Comput. Surveys, vol. 14, pp. 473-530, Sept. 1982.
    • (1982) ACM Comput. Surveys , vol.14 , pp. 473-530
    • Smith, A.J.1
  • 3
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • May
    • N. P. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers," in Proc. 17th Annu. Int. Sympo. Computer Architecture, May 1990, pp. 364-373.
    • (1990) Proc. 17th Annu. Int. Sympo. Computer Architecture , pp. 364-373
    • Jouppi, N.P.1
  • 7
    • 0026267802 scopus 로고
    • An effective on-chip preloading scheme to reduce data access penalty
    • Nov.
    • J.-L. Baer and T.-F. Chen, "An effective on-chip preloading scheme to reduce data access penalty," in Proc. Supercomputing'91, Nov. 1991, pp. 176-186.
    • (1991) Proc. Supercomputing'91 , pp. 176-186
    • Baer, J.-L.1    Chen, T.-F.2
  • 8
    • 0029308368 scopus 로고
    • Effective hardware-based data prefetching for high-performance processors
    • May
    • T.-F. Chen and J.-L. Baer, "Effective hardware-based data prefetching for high-performance processors," IEEE Trans. Comput., vol. 44, pp. 318-328, May 1995.
    • (1995) IEEE Trans. Comput. , vol.44 , pp. 318-328
    • Chen, T.-F.1    Baer, J.-L.2
  • 9
    • 0344300562 scopus 로고
    • Prefetch unit for vector operations on scalar computers
    • Sept.
    • I. Sklenar, "Prefetch unit for vector operations on scalar computers," ACM Comput. Architec. News, vol. 20, pp. 31-37, Sept. 1992.
    • (1992) ACM Comput. Architec. News , vol.20 , pp. 31-37
    • Sklenar, I.1
  • 11
    • 0026918402 scopus 로고
    • Design and evaluation of a compiler algorithm for prefetching
    • Sept.
    • T. Mowry, M. Lam, and A. Gupta, "Design and evaluation of a compiler algorithm for prefetching," in SIGPLAN Notices, Sept. 1992, pp. 62-73.
    • (1992) SIGPLAN Notices , pp. 62-73
    • Mowry, T.1    Lam, M.2    Gupta, A.3
  • 12
    • 0028202735 scopus 로고
    • A performance study of software and hard-ware data prefetching schemes
    • Apr.
    • T.-F. Chen and J.-L. Baer, "A performance study of software and hard-ware data prefetching schemes," in Proc. 21st Int. Symp. Computer Architecture, Apr. 1994, pp. 223-232.
    • (1994) Proc. 21st Int. Symp. Computer Architecture , pp. 223-232
    • Chen, T.-F.1    Baer, J.-L.2
  • 16
    • 0030416716 scopus 로고    scopus 로고
    • Memory hierarchy synthesis of a multimedia embedded processor
    • Oct.
    • S. T. Fu, D. F. Zucker, and M. J. Flynn, "Memory hierarchy synthesis of a multimedia embedded processor," in Proc. Int. Conf. Computer Design, Oct. 1996 , pp. 176-184.
    • (1996) Proc. Int. Conf. Computer Design , pp. 176-184
    • Fu, S.T.1    Zucker, D.F.2    Flynn, M.J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.