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Volumn 16, Issue 3, 2000, Pages 197-216

On interaction between interconnection network design and latency hiding techniques in multiprocessors

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; CHANNEL CAPACITY; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); INTERCONNECTION NETWORKS; RESOURCE ALLOCATION; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION TRAFFIC;

EID: 0034229872     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008113009823     Document Type: Article
Times cited : (1)

References (32)
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    • Karol, M.J.1    Hluchyj, M.G.2    Morgan, S.P.3
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    • Kermani, P.1    Kleinrock, L.2
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  • 22
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    • Leiserson, C.1
  • 23
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    • Tolerating latency through software-controlled prefetching in shared-memory multiprocessors
    • June
    • T. Mowry and A. Gupta. Tolerating latency through software-controlled prefetching in shared-memory multiprocessors. Journal of Parallel and Distributed Computing, pp. 87-106, June 1991.
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    • Mowry, T.1    Gupta, A.2
  • 24
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    • Design and analysis of even-sized binary shuffle-exchange networks for multiprocessor
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    • K. Padmanabhan. Design and analysis of even-sized binary shuffle-exchange networks for multiprocessor. IEEE Transactions on Parallel and Distributed Systems, 2(4):385-397, October 1991.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.