A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 μm technology node and beyond

IEEE Transactions on Electron Devices

Volumn 47, Issue 7, 2000, Pages 1499-1506

  Ha, Daewon ^a,b   Shin, Dongwon ^b   Koh, Gwan Hyeob ^b   Lee, Jaegu ^b   Lee, Sanghyeon ^b   Ahn, Yong Seok ^b   Jeong, Hongsik ^b   Chung, Taeyoung ^b   Kim, Kinam ^b  

^a Samsung Electronics Company ^*

^b SAMSUNG Electronics   (South Korea)

Author keywords

Alumina; Chemical mechanical polishing; Dual thickness gate oxide; Dual work function gate; Embedded DRAM; Hemispherical grain; Nitride liner; Planarization; Self aligned contact; Silicidation; Stacked cell capacitor; Titanium suicide; Tungsten bit line

Indexed keywords

DUAL THICKNESS GATE OXIDE; MEMORY CELL EFFICIENCY; NITRIDE LINER; NOISE IMMUNITY; POWER CONSUMPTION; SELF ALIGNED CONTACT ETCHING; SILICIDATION; SMALL FOOT PRINT CHIP; STACKED CELL CAPACITOR; TITANIUM POLYCIDE;

ALUMINA; CAPACITORS; COST EFFECTIVENESS; DYNAMIC RANDOM ACCESS STORAGE; ETCHING; LITHOGRAPHY; POLISHING; SEMICONDUCTOR JUNCTIONS; SILICON NITRIDE; SILICON ON INSULATOR TECHNOLOGY; TITANIUM COMPOUNDS; TUNGSTEN;

TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

EID: 0034228671     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.848299     Document Type: Article

References (25)

1. K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and challenges of multigigabit DRAM chip design,"IEEE J. Solid-State Circuits, vol. 32, pp. 624-634, May 1997.
2. S. Crowder et al., "Integration of trench DRAM into a high-performance 0.18 μm logic technology with copper BEOL," in IEDM TechDig., 1998, pp. 1017-1020.
3. S. Lyer and H. Kalter, "Embedded DRAM technology: Opportunities and challenges," IEEE Spectrum, vol. 36, pp. 56-64, 1999.
4. J. Borel, "Technologies for multimedia systems on a chip," in ISSCC Tech. Dig., 1997, pp. 18-21.
5. H. Ishiuchi et al., "Embedded DRAM technologies," in IEDM TechDig., 1997, pp. 33-36.
6. P. Bichebois, "Impact of physical defects on the electrical working of embedded DRAM with 0.35 μm design rules," in Proc. Defect and Fault Tolerance in VLSI Systems, 1996, pp. 124-130.
7. K. Kim, C.-G. Hwang, and J. G. Lee, "DRAM technology perspective for gigabit era," IEEE Trans. Electron Devices, vol. 45, pp. 598-608, Mar. 1998.
8. K. N. Kim et al., "A 0.15 μm DRAM technologynode for 4Gb DRAM," in VLSI Technology DigTech. Papers, June 1998, pp. 16-17.
9. H. Koike et al., "Fully integrated embedded DRAM technologies with high performance logic and commdity DRAM cells for system-on-a-chip," in ProcVLSI Technology, Systems, and Applications, 1999, pp. 243-246.
10. S. Crowder et al., "Trade-offs in the integration of high performance devices with trench capacitor DRAM," in IEDM TechDig., 1997, pp. 45-48.
11. M. Yoshida et al., "Low temperature metal-based cell integration technology for gigabit and embedded DRAMs," in IEDM TechDig., 1997, pp. 41-444.
12. A. Nitayama, Y. Kohyama, and K. Hieda, "Future directions for DRAM memory cell technology," in IEDM Tech. Dig., 1998, pp. 355-358.
13. S. Nakamura et al., "Embedded DRAM technology compatible to the 0.13 μm high-speed logics by using Ru pillars in cell capacitors and peripheral vias," in IEDM TechDig., 1998, pp. 1029-1031.
14. S. Sim et al., "A new planar stacked technology (PST) for scaled and embedded DRAMs," in IEDM TechDig., 1996, pp. 597-600.
15. B. Doyle, H. Soleimani, and A. Philipossian, "Simultaneous growth of different thickness gate oxides in silicon CMOS processing," IEEE Trans. Electron Device Lett., vol. 16, pp. 301-302, 1995.
16. M. Togo, K. Noda, and T. Tanigawa, "Multiple thickness gate oxide and dual gate technologies for high performance logic-embedded DRAMs," in IEDM Tech. Dig., 1998, pp. 347-350.
17. P. Wright and K. Saraswat, "The effect of fluorine in silicon dioxide gate dielectrics," IEEE Trans. Electron Devices, vol. 36, pp. 879-889, May 1989.
18. 4-sidewall (DSS) for high performance logic-embedded DRAM's," in IEDM TechDig., 1997, pp. 37-40.
19. D. Shin et al., "Fully planarized process integration and its effects on the process margin for 0.15-micron DRAM technology," JKorean Phys. Soc., vol. 35, pp. S815-S819, Dec. 1999.
20. Y. Y. Chen et al., "Performance and reliability assessment of dual-gate CMOS devices with gate oxide grown on nitrogen implanted Si substrates," in IEDM TechDig., 1997, pp. 639-642.
21. L. K. Han et al., "Electrical characteristics and reliability of Sub-3 nm gate oxides grown on nitrogen implanted silicon substrates," in IEDM TechDig., 1997, pp. 643-646.
22. 2 - Significant improvement of charge-to-breakdown distribution tail-," in Proc. 1999 Int. Reliab. Phys. Symp., San Diego, CA, 1999, pp. 93-98.
23. M. Ushiyama, A. Satoh, and H. Kume, "Suppression of anomalous leakage current in tunnel oxides by fluorine implantation to realize highly reliable flash memory," in VLSI Technology Dig. Tech. Papers, June 1999, pp. 23-24.
24. 3/poly-Si capacitor for high density DRAMs," in VLSI Technology DigTech. Papers, June 1998, pp. 52-53.
25. W. S. Yang et al., "Novel integration technology with capacitor over metal (COM) by using self-aligned dual damascene (SADD) process for 0.15 μm stand-alone and embedded DRAMs," in VLSI TechDig. Tech. Papers, June 1999, pp. 13-14.