Chip scale package issues

Microelectronics Reliability

Volumn 40, Issue 7, 2000, Pages 1157-1161

  Ghaffarian, Reza ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; RELIABILITY; SOLDERED JOINTS;

CHIP SCALE PACKAGES (CSP);

ELECTRONICS PACKAGING;

EID: 0034226652     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(00)00041-X     Document Type: Article

References (3)

1. Ghaffarian R. Ball Grid Array Packaging Guidelines, distributed by Interconnection Technology Research Institute (ITRI), 1998, http://www.ITRI.org
2. Ghaffarian R, et al. CSP Consortia Activities: Program Objectives and Status, Surface Mount International Proceedings, 1998. p. 203-30.
3. Ghaffarian R. Chip Scale Packaging Guidelines, distributed by Interconnection Technology Research Institute (ITRI), 2000, http://www.ITRI.org