Parasitic extraction methodology for insulated gate bipolar transistors

IEEE Transactions on Power Electronics

Volumn 15, Issue 4, 2000, Pages 799-804

  Trivedi, Malay ^a,b   Shenai, Krishna ^a,b  

^a IEEE

^b 1120 Science and Engineering Offices   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC IMPEDANCE MEASUREMENT; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; SEMICONDUCTOR DIODES; SWITCHING NETWORKS; TWO DIMENSIONAL;

EMITTER INDUCTANCE; INSULATED GATE BIPOLAR TRANSISTOR; PARASITIC EXTRACTION; ZERO CURRENT SWITCHING; ZERO VOLTAGE;

BIPOLAR TRANSISTORS;

EID: 0034226313     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/63.849051     Document Type: Article

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