First results of ITC'99 benchmark circuits

IEEE Design and Test of Computers

Volumn 17, Issue 3, 2000, Pages 54-59

  Basto, Luis ^a,b  

^a ANALOG DEVICES INC   (United States)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATOR; BENCHMARK CIRCUIT; ELECTRONIC DESIGN AUTOMATION; REGISTER TRANSFER LEVEL; VERILOG HARDWARE DESCRIPTION LANGUAGE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TESTING; BENCHMARKING; COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DESIGN FOR TESTABILITY; EQUIVALENT CIRCUITS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; SHIFT REGISTERS;

COMPUTER CIRCUITS;

EID: 0034224167     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.867895     Document Type: Article

References (2)

1. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits," Proc. IEEE Int'l Symp. Circuits and Systems, IEEE Press, Piscataway, N.J., 1985, pp. 695-698.
2. F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. IEEE 1989 Int'l Symp. Circuits and Systems, IEEE Press, Piscataway, N.J., May 1989, pp. 1924-1934.