Process development for 30 nm poly gate patterning on 1.2 nm oxide

Microelectronic Engineering

Volumn 53, Issue 1, 2000, Pages 159-162

  Heitzmann, M ^a   Nier, M E ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CORROSION PREVENTION; ELECTRIC PROPERTIES; ETCHING; GATES (TRANSISTOR); MASKS; PHOTORESISTS; POLYSILANES; SUBSTRATES;

ELECTRICAL PERFORMANCE; POLY GATE PATTERNING; POLYSILICON;

MOSFET DEVICES;

EID: 0034206215     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(00)00286-0     Document Type: Article

References (1)

1. 1. X-ray Photoelectron Analysis of Sidewall Passivation Films Formed During Sub 0.1 μm Silicon Gate Etch Processes. L. Desvoivres, France Telecom-CNET, L. Vallier, O. Joubert, France Telecom-CNET and CNRS. AVS Symposium, Seattle, Washington, October 25-2, 1999