Synthesizable HDL generation for pipelined processors from a micro-operation description

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E83-A, Issue 3, 2000, Pages 394-399

  Itoh, Makiko ^a   Takeuchi, Yoshinori ^b   Imai, Masaharu ^a   Shiomi, Akichika ^b  

^a OSAKA UNIVERSITY   (Japan)

^b SHIZUOKA UNIVERSITY   (Japan)

Author keywords

HDL generation; Instruction set processor; Micro operation description; Pipelined processor

Indexed keywords

COMPUTER GRAPHICS; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; DISCRETE TIME CONTROL SYSTEMS; IMAGE PROCESSING; MOS DEVICES; NEURAL NETWORKS; PETRI NETS; PHASE LOCKED LOOPS; PIPELINE PROCESSING SYSTEMS; SECURITY OF DATA; VLSI CIRCUITS; COMPUTER ARCHITECTURE; DATA TRANSFER; FORMAL LOGIC; PROGRAM PROCESSORS;

DIGITAL IMAGES; EIREV; GENERALIZED LOGISTIC MAP; WAVELET BASED WATERMARKING; WAVELET FILTERS;

INTEGRATED CIRCUIT MANUFACTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES;

INSTRUCTION SET PROCESSOR; MICRO OPERATION DESCRIPTION; PIPELINED PROCESSOR;

EID: 0034147214     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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