Cut-based functional debugging for programmable systems-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 1, 2000, Pages 40-51

  Kirovski, Darko ^a   Potkonjak, Miodrag ^a   Guerra, Lisa M ^b  

^a Engineering IV   (United States)

^b Bevocal   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION;

EMULATION; PROGRAMMABLE SYSTEMS-ON-CHIP;

VLSI CIRCUITS;

EID: 0034135634     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.820760     Document Type: Article

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