TEM/CBED determination of strain in silicon-based submicrometric electronic devices

Micron

Volumn 31, Issue 3, 2000, Pages 203-209

  Armigliato, A ^a   Balboni, R ^a   Balboni, S ^a   Frabboni, S ^b   Tixier, A ^c   Carnevale, G P ^d   Colpani, P ^d   Pavia, G ^d   Marmiroli, A ^d  

^a CNR   (Italy)

^b UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^c Institut Superieur de l'Electronique et du Numerique   (France)

^d STMICROELECTRONICS   (Italy)

Author keywords

Convergent beam electron diffraction (CBED); Cross sections; Local isolation structures (LOCOS); Process Simulation codes; Strain tensor; Submicron devices; Transmission electron microscopy (TEM)

Indexed keywords

EID: 0034093187     PISSN: 09684328     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0968-4328(99)00084-0     Document Type: Conference Paper

References (11)

1. 4 stripes. Comparison between ATHENA calculation and TEM/CBED measurements. Solid State Phenomena. 57/58:1997;365-370.
2. Baccus, B., Collard, D., Ferreira, P., Senez, V., Vandenbossche, E., 1996. IMPACT-4.8.1: Isen Modeling Package For Integrated Circuit Technology, Version 4.8.1.
3. Balboni R., Frabboni S., Armigliato A. Determination of bulk mismatch values in transmission electron microscopy cross sections of heterostructures by convergent-beam electron diffraction. Phil. Mag. A. 77:1998;67-83.
4. Deal B.E., Grove S.A. General relationship for the thermal oxidation of silicon. J. Appl. Phys. 36:1965;3770-3778.
5. Hu S.M. Stress-related problems in silicon technology. J. Appl. Phys. 70:1991;R53-R80.
6. Jones P.M., Rackham G.M., Steeds J.W. Higher order Laue zone effects in electron diffraction and their use in lattice parameter determination. Proc. R. Soc. Lond. A. 354:1977;197-222.
7. Kao D.B., McVittie J.P., Nix W.D., Saraswat K.C. Two-dimensional thermal oxidation of silicon - II. Modeling stress effects in wet oxides. IEEE Trans. Electron. Dev. ED-35:1988;25-38.
8. Silvaco International, 1996. ATHENA User's Manual, 2D Process Simulation Software.
9. Smeys, P., Griffin, P.B., Rek, Z.U., deWolf, I., Saraswat, K.C., 1996. The effects of process-induced stress on junction leakage and its impact on the scalability of isolation structures. Proc. IEDM'96, San Francisco, pp. 709-712.
10. Tixier, A., 1998. Etude et caracterisation de structures d'isolement de type LOCOS pour une Technologie CMOS 0.35 μm, PhD Thesis.
11. 7-δ from nanometer-sized region. Ultramicroscopy. 41:1992;211-223.