Inductive noise reduction at the architectural level

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 162-167

  Pant, Mondira Deb ^a   Pant, Pankaj ^a   Wills, Donald Scott ^a   Tiwari, Vivek ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENT CONTROL; ELECTRIC POWER SUPPLIES TO APPARATUS; IMAGE PROCESSING; MICROCOMPUTERS; VOLTAGE CONTROL;

CHIP POWER CONSUMPTION; CRITICAL SYSTEM PARAMETER; FUNCTIONAL BLOCKS; GIGASCALE INTEGRATION; GROUND BOUNCE CURRENT; INDUCTIVE NOISE REDUCTION; SOFTWARE PACKAGE SPICE; VOLTAGE SCALING;

COMPUTER ARCHITECTURE;

EID: 0033886675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)