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Volumn 40, Issue 2, 2000, Pages 191-206

Perspectives on giga-bit scaled DRAM technology generation

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; LEAKAGE CURRENTS; METALLIZING; THRESHOLD VOLTAGE;

EID: 0033880334     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2714(99)00220-6     Document Type: Review
Times cited : (31)

References (31)
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    • A new memory cell technology using merged process with storage node and storage node contact process in COB stacked cell for 4 Gb DRAM and beyond
    • Chun YS, Park BJ, Kwak DH, Hwang YS, Jeong GT, Chung TY, Kim Kinam. A new memory cell technology using merged process with storage node and storage node contact process in COB stacked cell for 4 Gb DRAM and beyond. In: Technical digest of 98 IEDM. 1998. p. 351-41.
    • (1998) Technical Digest of 98 IEDM , pp. 351-441
    • Chun, Y.S.1    Park, B.J.2    Kwak, D.H.3    Hwang, Y.S.4    Jeong, G.T.5    Chung, T.Y.6    Kim, K.7
  • 7
    • 0018059603 scopus 로고
    • Novel high density, stacked capacitor MOS RAM
    • 1978 IEEE IEDM
    • Koyanagi M, Sunami H, Hashimoto N, Ashikawa M. Novel high density, stacked capacitor MOS RAM. In: Digest, 1978 IEEE IEDM. 1978. p. 348-51.
    • (1978) Digest , pp. 348-351
    • Koyanagi, M.1    Sunami, H.2    Hashimoto, N.3    Ashikawa, M.4
  • 18
    • 0000561066 scopus 로고    scopus 로고
    • Self-aligned local channel implantation using reverse gate pattern for deep submicron DRAM cell transistors
    • Ha Daewon, Sim Jai-hoon, Kim Kinam. Self-aligned local channel implantation using reverse gate pattern for deep submicron DRAM cell transistors. Jpn J Appl Phys 1998;37:1059-63.
    • (1998) Jpn J Appl Phys , vol.37 , pp. 1059-1063
    • Ha, D.1    Sim, J.-H.2    Kim, K.3
  • 19
    • 0029490113 scopus 로고
    • Well concentration: A novel scaling limitation factor derived from DRAM retention time and its modeling
    • Hamamoto T, Sugiura S, Sawada S. Well concentration: A novel scaling limitation factor derived from DRAM retention time and its modeling. In: IEDM Tech. Digest. 1995. p. 915-8.
    • (1995) IEDM Tech. Digest , pp. 915-918
    • Hamamoto, T.1    Sugiura, S.2    Sawada, S.3
  • 20
    • 0032652485 scopus 로고    scopus 로고
    • High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's
    • Sim Jai-hoon, Lee Jae-Kyu, Kim Kinam. High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's. TED 1999;46(6): 1212-7.
    • (1999) TED , vol.46 , Issue.6 , pp. 1212-1217
    • Sim, J.-H.1    Lee, J.-K.2    Kim, K.3
  • 25
    • 0031118260 scopus 로고    scopus 로고
    • Characteristics of very high-aspect-ratio contact hole etching
    • Part I
    • Ikegami N, Yabata A, Matusui T, Kanamori J, Horiike Y. Characteristics of very high-aspect-ratio contact hole etching. Jpn J Appl Phys 1997;36(4B):2470-6 Part I.
    • (1997) Jpn J Appl Phys , vol.36 , Issue.4 B , pp. 2470-2476
    • Ikegami, N.1    Yabata, A.2    Matusui, T.3    Kanamori, J.4    Horiike, Y.5
  • 29
    • 0029547914 scopus 로고
    • Interconnect scaling-the real limiter to high performance ULSI
    • Mark T Bohr. Interconnect scaling-the real limiter to high performance ULSI. In: IEDM Tech. Digest. 1995. p. 241-4.
    • (1995) IEDM Tech. Digest , pp. 241-244
    • Bohr, M.T.1
  • 31
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    • Copper-based metallization in ULSI structure
    • Li J, Seidel TE, Mayer JW. Copper-based metallization in ULSI structure. MRS Bulletin 1994;XIX(8):15-21.
    • (1994) MRS Bulletin , vol.19 , Issue.8 , pp. 15-21
    • Li, J.1    Seidel, T.E.2    Mayer, J.W.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.