Interconnect scaling scenario using a chip level interconnect model

IEEE Transactions on Electron Devices

Volumn 47, Issue 1, 2000, Pages 90-96

  Yamashita, Kyoji ^a   Odanaka, Shinji ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; DIELECTRIC MATERIALS; LSI CIRCUITS; MATHEMATICAL MODELS;

INTERCONNECT SCALING SCENARIO; REPEATER BUFFERS; VARIABLE PITCH ROUTER;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033880144     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.817572     Document Type: Article

References (15)