High-speed low-power complex matched filter for w-cdma: algorithm and vlsi-architecture

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E83-A, Issue 1, 2000, Pages 150-157

  Chen, Jie ^a,b   Shou, Guoliang ^a   Zhou, Changming ^a  

^a YOZAN Inc   (Japan)

^b UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

Matched filter; Mixed signal lsi; Parallel analog operational circuit; Weighted sum operation

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; QUADRATURE PHASE SHIFT KEYING; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

MATCHED FILTERS; WIDEBAND CODE DIVISION MULTIPLE ACCESS (W-CDMA) COMMUNICATIONS;

CODE DIVISION MULTIPLE ACCESS;

EID: 0033878989     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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