Low power realization of residue number system based FIR filters

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 30-33

  Mahesh, M N ^a   Mehendale, Mahesh ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; MATHEMATICAL TRANSFORMATIONS; PARALLEL PROCESSING SYSTEMS; VOLTAGE CONTROL;

COEFFICIENT ENCODING; COEFFICIENT ORDERING; LOW POWER REALIZATION; POWER DISSIPATION; POWER REDUCTION; RESIDUE NUMBER SYSTEM; SOFTWARE PACKAGE SPICE; SWITCHED CAPACITANCE REDUCTION; VOLTAGE SCALING;

FIR FILTERS;

EID: 0033878898     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)