Modeling of transition metal redistribution to enable wafer design for gettering

Journal of the Electrochemical Society

Volumn 147, Issue 3, 2000, Pages 1154-1160

  Smith, A L ^a   Wada, K ^a   Kimerling, L C ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIFFUSION; GETTERS; HEAT TREATMENT; INTEGRATED CIRCUIT LAYOUT; SEGREGATION (METALLOGRAPHY); SILICON WAFERS; SOLUBILITY; TEMPERATURE;

INTERNAL GETTERING; TRANSITION METAL REDISTRIBUTION; WAFER DESIGN;

IRON;

EID: 0033871383     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1393329     Document Type: Article

References (19)

1. T. E. Seidel, R. L. Meek, and A. G. Cullis, J. Appl. Phys., 46, 600 (1975).
2. H. Reiss and C. S. Fuller, J. Met., 12, 276 (1956).
3. H. M'saad, Ph.D. Thesis, Massachusetts Institute of Technology, Cambridge, MA (1994).
4. J. L. Benton, P. A. Stolk, D. J. Eaglesham, D. C. Jacobson, J.-Y. Cheng, and J. M. Poate, J. Appl. Phys., 80 3275 (1996).
5. L. L. Chalfoun, M.S. Thesis, Massachusetts Institute of Technology, Cambridge, MA (1996).
6. S. Zhao, A. L. Smith, S. H. Ahn, G. J. Norga, M. T. Platero, H. Nakashima, L. V. C. Assali, J. Michel, and L. C. Kimerling, in The 19th International Conference on Defects in Semiconductors, Materials Science Forum, July 21-25, 1997, Aveiro, Portugal (1997).
7. K. Wada, Phys. Rev. B, 30, 5884 (1984).
8. M. Hourai, K. Murakami, T. Shigematsu, N. Fujino, and T. Shiraiwa, Jpn. J. Appl. Phys, 28, 2413 (1989).
9. L. C. Kimerling and J. L. Benton, Physica B, 116, 297 (1983).
10. M. A. Green, J. Appl. Phys., 67, 2944 (1990).
11. R. A. Smith, Semiconductors, 2nd ed., Cambridge University Press, London (1979).
12. D. Gilles, W. Schroeter, and W. Bergholtz, Phys. Rev. B, 41, 5770 (1990).
13. A. L. Smith, S. T. Dunham, and L. C. Kimerling, Physica B, 273-4, 356 (1999).
14. E. R. Weber, Appl. Phys. A, 30, 1 (1983).
15. T. Y. Tan, R. Gafiteanu, and U. Goesele, in The NREL 6th Workshop an the Role of Impurities and Defects in Silicon Device Processing, p. 116, Snowmass, CO, Aug 12-14, 116 (1996).
16. S. H. Ahn, S. Zhao, A. L. Smith, L. L. Chalfoun, H. Nakashima, M. T. Platero, and L. C. Kimerling, Mater. Res. Soc. Symp. Proc., 442, 169 (1997).
17. D. Gilles, E. R. Weber, and S. Hahn, Phys. Rev. Lett., 64, 196 (1990).
18. D. A. Antoniadis and R. Dutton, IEEE Trans. Electron. Devices, ED-26, 490 (1990).
19. T. Y. Tan, R. Gafiteanu, and U. Goesele, in The NREL 5th Workshop on the Role of Impurities and Defects in Silicon Device Processing, p. 93, Copper Mountain, CO, Aug 13-16, 1995.