Phase noise up-conversion reduction for integrated CMOS VCOs

Electronics Letters

Volumn 36, Issue 10, 2000, Pages 857-858

  Borremans, M ^a   De Muer, B ^a   Steyaert, M ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; POWER INDUCTORS; SPURIOUS SIGNAL NOISE;

INTEGRATED PLANAR INDUCTORS; PHASE NOISE UP-CONVERSION REDUCTIONS;

VARIABLE FREQUENCY OSCILLATORS;

EID: 0033749874     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000655     Document Type: Article

References (4)

1. LEE, J., KRAL, A., and ABIDI, A.: 'Design of spiral inductors on silicon substrates with a fast simulator'. Proc. IEEE ESSCIRC'98 Conf., Sept. 1998, pp. 328-331
2. MOHAN, S.S., DEL MAR HERSHENSON, M., BOYD, S.P., and LEE, T.H.: 'Simple accurate expression for planar spiral inductances', IEEE J. Solid-State Circuits, 1999, SC-34, (10), pp. 1419-1424
3. POST, J.E., LINSCOTT, I.R., and OSLICK, M.H.: 'Waveform symmetry properties and phase noise in oscillators', Electron. Lett., 1998, 34, (16), pp. 1547-1548
4. DE MUER, B., ITOH, N., BORREMANS, M., and STEYAERT, M.: 'A 1.8 GHz highly-tunable low-phase-noise CMOS VCO'. To be published in IEEE CICC 2000 Conf. Proc., Orlando, May 2000