Use of test structures for Cu interconnect process development and yield enhancement

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2000, Pages 63-66

  Skumanich, Andy ^a   Cai, Man ping ^a   Educato, James ^a   Yost, Dennis ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL POLISHING; COPPER; DEFECTS; ETCHING; LITHOGRAPHY; PROCESS CONTROL; SCANNING ELECTRON MICROSCOPY;

AUTOMATIC DEFECT CLASSIFICATION; DUAL DAMASCENE PROCESS;

INTEGRATED CIRCUIT TESTING;

EID: 0033726579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)