A diagnostic test generation procedure based on test elimination by vector omission for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 5, 2000, Pages 589-600

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

Fault diagnosis; Synchronous sequential circuits

Indexed keywords

DICTIONARY STORAGE; FAULT DETECTION; STUCK AT FAULT; SYNCHRONOUS SEQUENTIAL CIRCUITS;

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ERROR DETECTION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; SET THEORY; VECTORS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0033726337     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.845083     Document Type: Article

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