Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 762-767

  Katagiri, Hisaaki ^a   Yasumoto, Keiichi ^a   Kitajima, Akira ^a   Higashino, Teruo ^a   Taniguchi, Kenichi ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FINITE AUTOMATA; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MATHEMATICAL MODELS; NETWORK PROTOCOLS; SYNCHRONIZATION; TIMING CIRCUITS;

FINITE STATE MACHINE; HARDWARE CIRCUIT; HIGH LEVEL SYNTHESIS; MULTIWAY SYNCHRONIZATION;

LOGIC DESIGN;

EID: 0033725719     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/337292.337771     Document Type: Conference Paper

References (15)