High-speed, low-complexity FIR filter using multiplier block reduction and polyphase decomposition

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages

  Martinez Peiro, Marcos ^a   Wanhammar, Lars ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTERPOLATION; MULTIPLYING CIRCUITS;

CARRY SAVE ADDERS; DECIMATION;

FIR FILTERS;

EID: 0033725372     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856073     Document Type: Conference Paper

References (10)