Pipeline parallel architecture for a fuzzy inference processor

IEEE International Conference on Fuzzy Systems

Volumn 1, Issue , 2000, Pages 257-262

  Ascia, Giuseppe ^a   Catania, Vincenzo ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INFERENCE ENGINES; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

FUZZY LOGIC INFERENCES PER SECOND (FLIPS);

FUZZY SETS;

EID: 0033722124     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)