On-Chip Interconnect Lines with Patterned Ground Shields

IEEE Microwave and Guided Wave Letters

Volumn 10, Issue 2, 2000, Pages 49-51

  Lowther, Rex ^a   Lee, Sang Gug ^b  

^a INTERSIL CORPORATION   (United States)

^b School of Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC IMPEDANCE; ELECTRIC SHIELDING; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; TRANSMISSION LINE THEORY;

ON-CHIP INTERCONNECT LINES; PATTERNED GROUND SHIELDS;

MICROWAVE INTEGRATED CIRCUITS;

EID: 0033720299     PISSN: 10518207     EISSN: None     Source Type: Journal    
DOI: 10.1109/75.843097     Document Type: Article

References (5)

1. S. Seki and H. Hasegawa, “Cross-tie slow-wave coplanar waveguide on semi-insulating GaAs substrates,” Electron. Lett., vol. 17, no. 25, p. 940, Dec. 1981.
2. T. Wang and T. Itoh, “Compact grating structure for application to filters and resonators inmonolithic microwave integrated circuits,” IEEE Trans. Microwave Theory Tech., vol. MTT-35, p. 1176, Dec. 1987.
3. R. Lowther, “Integrated circuit with an improved inductor structure and method of fabrication,” U.S. Patent 5 717 243, Filed Apr. 24, 1996, issued Feb. 10, 1998.
4. C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned ground shields For Si-based RF IC's,” IEEE J. Solid State Circuits, vol. 33, p. 743, May 1998.
5. Y. Eo and W. R. Eisenstadt, “S-parameter-based IC interconnect transmission line characterization,” IEEE Trans. Comp. Hybrids, Manuf. Technol., vol. 15, p. 555, Aug. 1992.