On the issues of oscillation test methodology

IEEE Transactions on Instrumentation and Measurement

Volumn 49, Issue 2, 2000, Pages 240-245

  Wong, Mike Wai Tak ^a,b  

^a IEEE

^b HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CIRCUIT OSCILLATIONS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LINEAR INTEGRATED CIRCUITS; LOW PASS FILTERS; OPERATIONAL AMPLIFIERS;

ANALOG CIRCUITS; INTEGRATION FABRICATION TECHNOLOGY; OSCILLATION TEST METHODOLOGY; SELF TESTING;

ACTIVE FILTERS;

EID: 0033719083     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.843056     Document Type: Article

References (10)

1. A. E. Dunlop, W. J. Evans, and E. A. Rigge, "Managing complexity in IC design-Past, present, and future," Bell Labs Tech. J., pp. 103-125, Autumn 1997.
2. P. M. Dias, J. E. Franca, and N. Pauline, "Oscillation test methodology for a digitally-programmable switched-current biquad," in Proc. 2nd IEEE Int. Mixed Signal Testing Workshop, May 18, 1996, pp. 221-226.
3. K. Arabi, B. Kaminska, and S. Sunter, "Testing integrated operational amplifiers based on oscillation-test method," in Proc. 2nd IEEE Int. Mixed Signal Testing Workshop, May 18, 1996, pp. 227-232.
4. M. S. Zarnik, F Novak, and S. Macek, "Efficient go no-go test of active RC filters," Int. J. Circuit Theory Appl., vol. 26, pp. 523-529, 1998.
5. L. Milor and V. Visvanathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Trans. Computer-Aided Design, vol. 8, pp. 114-130, 1989.
6. S. Liu and L. W. Nagal, "Small-signal MOSFET models for analog circuit design," IEEE J. Solid-State Circuits, vol. SC-17, pp. 983-998, 1982.
7. A. Jee and F. J. Ferguson, "Carafe: An inductive fault analysis tool for CMOS/VLSI circuits," in Proc. IEEE VLSI Test Symp., 1993, pp. 92-98.
8. M. W. T. Wong, Y. Zhou, and Y. S. Lee, "Fault coverage improvement of linear analogue circuits based on error signal analysis," Int. J. Electron., vol. 84, no. 2, pp. 137-146, 1998.
9. Y. Zhou, M. W. T. Wong, and Y. Min, "On concurrent multiple error diagnosability in linear analog circuits using continuous checksum," Int. J. Circuit Theory Appl., vol. 26, no. 1, pp. 53-64, Jan.-Feb. 1998.
10. R. Jacob, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation. Piscataway, NJ: IEEE Press, 1998.