New metrics for architectural level power performance evaluation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2000, Pages

  Jia, Lihong ^a   Gao, Yonghong ^a   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT;

ARCHITECTURE-DRIVEN VOLTAGE SCALING LOW POWER DESIGN METHOD;

VLSI CIRCUITS;

EID: 0033718351     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856387     Document Type: Conference Paper

References (7)