Heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages

  Doboli, Alex ^a   Dhanwada, Nagu ^a   Vemuri, Ranga ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; HEURISTIC METHODS; ITERATIVE METHODS; SIGNAL PROCESSING;

ANALOG SYSTEMS; HIGH-LEVEL PERFORMANCE ESTIMATORS (HPE); SIGNAL-FLOW GRAPH (SFG);

COMPUTER ARCHITECTURE;

EID: 0033717845     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856026     Document Type: Conference Paper

References (9)