Wafer-level chip scale packaging: benefits for integrated passive devices

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 2, 2000, Pages 247-251

  Clearfield, Howard M ^a   Young, James L ^a   Wijeyesekera, Sunil D ^a   Logan, Elizabeth A ^a  

^a Intarsia Corp   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST BENEFIT ANALYSIS; FLIP CHIP DEVICES; PASSIVE NETWORKS; PRINTED CIRCUIT BOARDS; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS; WSI CIRCUITS;

BALL GRID ARRAY; CHIP SCALE PACKAGING; INTEGRATED PASSIVE DEVICES; WAFER LEVEL PROCESSING;

ELECTRONICS PACKAGING;

EID: 0033716847     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.846642     Document Type: Article

References (10)

1. H. M. Clearfield et ai, proc. 1998 Int. Conf. Multichip Modules High Density Interconnection, Denver, CO, 1998, p. 501.
2. R. G. Arnold, D. J. Redder, and C. C. Faulkner, proc. 6th Int. Conf. Multichip Modules, Denver, CO, 1977, p. 340.
3. P. Pieters, S. Brebels, and E. Beyne, proc. 6th Int. Conf. Multichip Modules, Denver, CO, 1997, p. 357.
4. R. C. Frye, P. R. Smith, and Y. E. Eow, Proc. Int. Conf. Multichip Modules High Density Packag., Denver, CO, 1997, p. 518.
5. J. Härtung, Proc. Int. Conf. Multichip Modules High Density Packag., Denver, CO, 1998, p. 273.
6. M. de Samber, N. Pulsford, M. van Delden, and R. Milsom, Proc. Int. Conf. Multichip Modules High Density Packag., Denver, CO, 1998, p. 304.
7. J. E. Young and E. A. Eogan, proc. 1999 IM APS Pan-Pacific Microelectron. Conf., Denver, CO, 1999.
8. S. D. Wijeyesekera, N. Patel, D. H. Bolton, P. Chang, and H. M. Clearfield, proc. 1999 Int. Conf. High Density Packag. Multichip Modules, Denver, CO, 1999, p. 450.
9. A. R. Mizra and A. A. Ayon, J. Appl. Sensing Tech., 1998.
10. S. D. Wijeyesekera, D. H. Bolton, N. Patel, and H. M. Clearfield, "Preliminary results on ball shear testing," . in preparation.