450Mbit/s parallel read/write channel with parity check and 16-state time variant viterbi

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 319-322

  Bollati, G ^a   Dati, A ^a   Betti, G ^a   Bietti, I ^a   Brianti, F ^a   Bruccoleri, M ^a   Coltella, M ^a   Demartini, P ^a   Demicheli, M ^a   Gadducci, P ^a   Marchese, S ^a   Ottini, D ^a   Pisati, V ^a   Rezzi, F ^a   Rossi, A ^a   et al , ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; BLOCK CODES; ELECTRIC LOSSES; LOW PASS FILTERS; MICROPROCESSOR CHIPS; TRELLIS CODES; VARIABLE FREQUENCY OSCILLATORS; WHITE NOISE;

MEDIA NOISE; OFF TRACK CONDITION; PARALLEL READ WRITE CHANNEL; PARITY CHECK TIME VARIANT VITERBI DETECTOR; WRITE FREQUENCY SYNTHESIZER;

CMOS INTEGRATED CIRCUITS;

EID: 0033716170     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)