Study of an elevated drain fabrication method for ultra-shallow junction

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 39, Issue 4 B, 2000, Pages 2155-2157

  Nakano, Masayuki ^a   Kotaki, Hiroshi ^a   Sugimoto, Kazuo ^a   Okumine, Tetsuya ^a   Yoshioka, Fumiyoshi ^a   Kakimoto, Seizo ^a   Ohta, Kenji ^a   Hashizume, Nobuo ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

Amorphous silicon; LSI; MOSFET; Polycrystalline silicon; Silicon; SIMS; Solid phase diffusion

Indexed keywords

AMORPHOUS SILICON; CHEMICAL VAPOR DEPOSITION; DIFFUSION IN SOLIDS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; LSI CIRCUITS; MASS SPECTROMETRY; MOSFET DEVICES; OXIDES; POLYCRYSTALLINE MATERIALS; SEMICONDUCTOR DEVICE MANUFACTURE; SUBSTRATES;

ELEVATED DRAIN FABRICATION; LOW CAPACITANCE SIDEWALL ELEVATED DRAIN; LOW PRESSURE CHEMICAL VAPOR DEPOSITION; POLYCRYSTALLINE SILICON; SOLID PHASE DIFFUSION; ULTRA SHALLOW METHOD;

SEMICONDUCTOR JUNCTIONS;

EID: 0033715108     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.39.2155     Document Type: Article

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