ALU design using a novel asynchronous pipeline architecture

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages

  Tang, Tin Yau ^a   Choy, Chiu Sing ^a   Butas, Jan ^a   Chan, Cheong Fat ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS;

ASYNCHRONOUS PIPELINE SYSTEMS;

ELECTRIC NETWORK SYNTHESIS;

EID: 0033713955     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857439     Document Type: Conference Paper

References (6)