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Volumn 36, Issue 12, 2000, Pages 1086-1088
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Design rules for buffering overlapping Pareto processes in packetized networks
a a a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
ELECTRIC NETWORK ANALYSIS;
ELECTRIC NETWORK SYNTHESIS;
MATHEMATICAL MODELS;
PARETO PRINCIPLE;
PROBABILITY;
BUFFER OVERFLOW;
LONG RANGE DEPENDENT PROCESSES;
PACKET NETWORKS;
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EID: 0033705218
PISSN: 00135194
EISSN: None
Source Type: Journal
DOI: 10.1049/el:20000757 Document Type: Article |
Times cited : (3)
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References (6)
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