Design of a quaternary latch circuit using a binary CMOS RS latch

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2000, Pages 377-381

  Current, K W ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE;

BINARY CMOS RS LATCH CIRCUIT; QUATERNARY LATCH CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033705129     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)