Parallel algorithms for FPGA placement

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2000, Pages 86-94

  Haldar, Malay ^a   Nayak, Anshuman ^a   Choudhary, Alok ^a   Banerjee, Prith ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; PARALLEL ALGORITHMS; SIMULATED ANNEALING;

VERSATILE PLACE AND ROUTE (VPR);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033703595     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/330855.330988     Document Type: Conference Paper

References (14)