New technique for estimating lower bounds on latency for high level synthesis

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2000, Pages 129-132

  Peixoto, Helvio P ^a   Jacome, Margarida F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; ESTIMATION;

DATA FLOW GRAPHS; HIGH LEVEL SYNTHESIS;

DIGITAL STORAGE;

EID: 0033699759     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)