Analog on-chip learning circuit architecture of the weight perturbation algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages

  Diotalevi, F ^a   Valle, M ^a   Bo, G M ^a   Biglieri, E ^a   Caviglia, D D ^a  

^a UNIVERSITY OF GENOA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

LEARNING ALGORITHMS; LEARNING SYSTEMS; PERTURBATION TECHNIQUES;

ON-CHIP LEARNING CIRCUITS;

VLSI CIRCUITS;

EID: 0033699545     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857120     Document Type: Conference Paper

References (12)