Compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2000, Pages

  Hatirnaz, I ^a   Gurkaynak, F K ^a   Leblebici, Y ^a  

^a WORCESTER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL FILTERS; FUNCTIONS; LOGIC GATES; NONLINEAR FILTERING; VECTORS;

BINARY SORTING ENGINES; CAPACITIVE THRESHOLD LOGIC GATES; RANK ORDER FILTERS;

SORTING;

EID: 0033699493     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.858844     Document Type: Conference Paper

References (11)