Spatial-temporal mapping of real applications on a dynamically reconfigurable logic engine (DRLE) LSI

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 151-154

  Furuta, Koichiro ^a   Fujii, Taro ^a   Motomura, Masato ^a   Wakabayashi, Kazutoshi ^a   Yamashina, Msakazu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD PROGRAMMABLE GATE ARRAYS; LARGE SCALE SYSTEMS; MATHEMATICAL TECHNIQUES;

DYNAMIC RECONFIGURABLE CAPABILITY; DYNAMICALLY RECONFIGURABLE LOGIC ENGINE; SPATIAL TEMPORAL MAPPING;

LOGIC DEVICES;

EID: 0033698305     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)