Timing-driven pseudo-exhaustive testing of VLSI circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2000, Pages

  Chang, S C ^a   Rau, J C ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION;

PSEUDO-EXHAUSTIVE TESTING;

VLSI CIRCUITS;

EID: 0033697581     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856292     Document Type: Conference Paper

References (16)